-- Quartus II VHDL Template
-- Basic Shift Register

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY TestRandom IS
	port 
	(
		Clk		: in std_logic;
		Reset	: in std_logic;
		sr_out	: out std_logic_vector(15 DOWNTO 0)
	);
END ENTITY;

ARCHITECTURE rtl OF TestRandom IS
	SIGNAL sr: std_logic_vector(62 DOWNTO 0);
BEGIN
	cm : PROCESS (Clk, Reset)
	BEGIN
		IF Reset = '0' THEN
			sr <= (OTHERS => '1');
		ELSIF rising_edge(Clk) THEN
			sr(62 DOWNTO 1) <= sr(61 DOWNTO 0);
			sr(0) <= sr(62) XOR sr(61);
		END IF;
	END PROCESS;
	sr_out <= sr(62 DOWNTO 47);
end rtl;
